Abstract: Our objective was to design a module that ensures the security of JTAG endpoints within the operational life cycle of a RISC-V processor system. Extensive research into the various aspects of JTAG and software led our team to adopt the Advanced Encryption Standard (AES) with counter-mode, effectively restricting unauthorized access. This approach adheres to the FIPS 140-3 standard, published by the National Institute of Standards and Technology (NIST) for security requirements of cryptographic modules. Our hardware-centric strategy is complemented by a software component named OpenOCD. The project concluded with a validated, secure JTAG interface, offering a reliable solution to safeguarding intellectual property.
Abstract: This project involved the designing, simulating, and testing of an AM transmitter and receiver using LTSPICE. The receiver was meticulously tuned to an 81.2 kHz carrier frequency, accommodating a message signal spanning 300 Hz to 3 kHz. Comprising a signal generator, switching modulator, and bandpass filter, the transmitter is seamlessly integrated with a receiver featuring a peak detector, a two-stage bandpass filter, a comparator, a buffer amplifier, and the speaker. Deviations from the theoretical expectations were observed, particularly with the predefined design requirements for the AM transmitter-receiver. This simulation project offers valuable insights into the conduct of similar electronic experiments in a physical lab setting.
